The present invention relates to the field of switching power supplies. More particularly, the present invention relates to switching power supplies that perform power factor correction using a carrier control and input voltage sensing.
Switching power supplies generally operate by modulating current from a power source using a switch. The switch is typically a transistor capable of handling significant current levels, such as a power metal oxide semiconductor field-effect transistor (MOSFET) or insulated gate bipolar transistor (IGBT). When the switch is closed, current passes through the switch, charging a reactive element with energy. When the switch is opened, the energy is discharged into a storage element, forming an output voltage. Opening and closing of the switch is generally controlled with feedback so as to regulate the output voltage at a constant level. The output voltage may be used to power a load or may be connected as an input to another power supply stage.
Some switching power supplies convert power from an alternating-current (AC) power source. Such a switching power supply may be referred to as an off-line power supply. An off-line power supply preferably presents a substantially resistive load to the AC source so as to avoid contaminating the AC source. In other words, the current drawn during the switching operations is substantially in phase with the voltage of the AC source. Power factor correction (PFC) is a technique for ensuring that the input current is in phase with the AC supply voltage.
There are generally two types of switching power supplies that perform power factor correction. A first type is known as average current-mode control. A circuit diagram of a switching power supply which performs power factor correction using average current-mode control is illustrated in FIG. 1. A line voltage is coupled to the input terminals of a full wave bridge rectifier 18. A first output terminal of the full wave bridge rectifier 18 is coupled to a first terminal of an inductor L1 and to a first input terminal of a multiplier 20. A second terminal of the inductor L1 is coupled to a drain of an NMOS transistor SW1 and to an anode of a diode SW2. A source of the NMOS transistor SW1 is coupled to the ground node.
A cathode of the diode SW2 is coupled to a first terminal of a capacitor C1 and to an output node Vout. A second terminal of the capacitor C1 is coupled to the ground node. Opening and closing of the transistor switch SW1 causes the current iL to flow in the inductor L1. The capacitor C1 is charged to a level which depends on the duty cycle at which the transistor switch SW1 is operated.
A first terminal of a resistor R1 is coupled to the output node Vout. A second terminal of the resistor R1 is coupled to a negative input of a error amplifier 10 and to a first terminal of a resistor R2. A second terminal of the resistor R2 is to the ground node. A positive input of the amplifier 10 is coupled to a reference voltage Vref. An output of the amplifier 10 forms an error signal which is representative of a difference between the output voltage Vout and a desired level for the output voltage Vout and is coupled to a second input of the multiplier 20.
An output of the multiplier 20 is coupled to a positive input terminal of a current error amplifier 22 and to a first terminal of a resistor Ra. A second terminal of the resistor Ra is coupled to a second output terminal of the full wave bridge rectifier 18 and to a first terminal of a sense resistor Rs. A second terminal of the sense resistor Rs is coupled to a first terminal of a resistor Rb and to the ground node. A second terminal of the resistor Rb is coupled to a negative input terminal of the amplifier 22. An output of the current error amplifier 22 is coupled to a negative input terminal of a modulating comparator 14. A linear periodic ramp output of the oscillator 12 is coupled to a positive input terminal of the modulating comparator 14. The ramp output of the oscillator 12 is formed by charging a capacitor with a constant current. An output of the modulating comparator 14 is coupled as an input R of a flip-flop 16. A clock output of the oscillator 12 is coupled as an input S of the flip-flop 16. An output Q of the flip-flop 16 is coupled to a gate of the NMOS transistor SW1.
A feed-forward signal from the full wave bridge rectifier 18 which senses the input voltage of the AC source is applied to one of the inputs of the multiplier 20. The other input to the multiplier 20 is the output of the voltage error amplifier 10.
The output of the multiplier 20 is a current which is the product of the reference current, the output of the voltage error amplifier 10 and a gain adjustor factor. This output current is applied to the resistor Ra. The voltage across the resistor Ra subtracts from the sensed voltage across the sense resistor Rs and is applied to the current error amplifier 22. Under closed loop control, the current error amplifier 22 will adjust the switching duty cycle try to keep this voltage differential near the zero volt level. This forces the voltage produced by the return current flowing through the sense resistor Rs to be equal to the voltage across the resistor Ra and, thus, forces the input current to follow the input voltage.
The amplified current error signal output from the current error amplifier 22 is then applied to the negative input to the modulating comparator 14. The other input to the modulating comparator 14 is coupled to receive the ramp signal output from the oscillator 12. Pulse width modulation is obtained when the amplified error signal that sets up the trip point modulates up and down. When compared to the linear ramp signal from the oscillator 12, this adjusts the switching duty cycle.
Thus, a current control loop modulates the duty cycle of the switch SW1 in order to force the input current to follow the waveform of the full wave rectified sine wave input voltage. The current control loop and the power delivery circuitry must have at least enough bandwidth to follow this waveform. The above-described average current-mode technique for power factor correction is characterized in that it requires AC input voltage sensing to obtain a sinusoidal reference signal, an analog multiplier to multiply this reference signal with the output voltage error signal, and a linear ramp signal formed by a constant current. By multiplying the AC input voltage sensing signal by the output voltage error signal, the input current is forced (by the amplifier 22 maintaining its inputs at equal voltage potential) to follow the input voltage in a tightly-controlled feedback loop. Thus, implementation of average current-mode control tends to require complex implementation which tends to increase the cost of such a switching power supply.
A second type of switching power supply that performs power factor correction is known as non-linear carrier control. A circuit diagram of a switching power supply which performs power factor correction using a non-linear carrier is illustrated in FIG. 2.
The switching power supply of FIG. 2 is described in an article by Dragan Maksimovic, Yungtaek Jang and Robert Erickson, entitled xe2x80x9cNonlinear-Carrier Control For High Power Factor Boost Rectifiers,xe2x80x9dEEE Transactions on Power Electronics, Vol. 11, No. 4, July 1996, pp. 578-584. The power factor controller proposed by Maksimovic et al. integrates the current through the switch and compares it with a non-linear parabolic carrier waveform in order to control the duty cycle of the switch. This eliminates the input voltage sensing, the current error amplifier and the linear ramp signal, which were all necessary in the power factor controller illustrated in FIG. 1.
The non-linear carrier controller 60 includes an integrator 80 for integrating the switch current Is and a carrier generator 74 for generating the non-linear carrier waveform Vc. An anode of a diode 62 is coupled to receive the switch current Is. A cathode of the diode 62 is coupled to a first terminal of a switch 64, to a first terminal of a capacitor 66 and to a positive input to a comparator 68, forming an output of the integrator 80 which provides the integrated signal Vq, representing the current flowing through the switch SW1. A second terminal of the switch 64 is coupled to a second terminal of the capacitor 66 and to ground.
A negative input to an adder circuit 78 is coupled to receive the output voltage Vo, representing the voltage delivered to the load. A positive input to the adder circuit 78 is coupled to receive a reference voltage Vref. A modulating output of the adder circuit 78 is coupled as an input to a voltage-loop error amplifier 76. An output Vm of the voltage-loop error amplifier 76 is coupled as an input to the carrier generator circuit 74. An output of the carrier generator circuit 74 provides the carrier waveform Vc and is coupled to a negative input to the comparator 68. An output of the comparator 68 is coupled to a reset input R of a flip-flop 70. An oscillator 72 provides a clock signal which is coupled to the carrier generator circuit 74 and to a set input S of the flip-flop 70. An inverted output Q of the flip-flop 70 is coupled to control the switch 64. An output Q of the flip-flop 70 is coupled as an input to the gate driver circuit 82. Together, the output Q of the flip-flop 70 and the gate driver circuit 82 control the operation of the switch SW1.
The integrated signal Vq is generated by the integrator 80 in response to the level of the current Is flowing through the switch SW1. The modulating output Vm of the voltage-loop error amplifier 76, representing the difference between the output voltage Vo and the reference voltage Vref, is input to the carrier generator 74 for generating the carrier waveform Vc. The comparator 68 compares the integrated signal Vq to the carrier waveform Vc. The output of the comparator 68 is at a logical low voltage level when the integrated signal Vq is less than the carrier waveform Vc. The output of the comparator 68 is at a logical high voltage level when the integrated signal Vq is greater than the carrier waveform Vc. The output of the comparator 68 is input to the flip-flop 70 and signals when the switch SW1 should be turned off. The oscillator clock signal generated by the oscillator 72 signals when the switch SW1 should be turned on. In this manner, the duty cycle of the switch SW1 is controlled by the nonlinear carrier controller illustrated in FIG. 2.
Other switching power supplies that perform power factor correction using a non-linear carrier are described in: U.S. Pat. No. 5,804,950, entitled, xe2x80x9cInput Current Modulation for Power Factor Correction;xe2x80x9d U.S. Pat. No. 5,742,151, entitled, xe2x80x9cInput Current Shaping Technique and Low Pin Count for PFC-PWM Boost Converter;xe2x80x9d and U.S. Pat. No. 5,798,635, entitled, xe2x80x9cOne Pin Error Amplifier and Switched Soft Start for an Eight Pin PFC-PWM Combination Integrated Circuit Converter Controller.xe2x80x9d
All of these power supplies which use non-linear carrier control, as in FIG. 2 and the above-mentioned patent documents, provide a simpler implementation for a power factor correction circuit than those that use average current-mode control, as in FIG. 2. They are characterized in that, rather than using ramp signal formed by a constant current as in FIG. 1, the carrier signal is based on the output error voltage signal (at the output of amplifier 76 in FIG. 2). And, the multiplier 20 of FIG. 1 is omitted. Because the shape of the carrier signal and, thus, the switching duty cycle, is determined based on the supply appearing as a resistive load, the input current only loosely follows the input voltage waveform. And, because under light load conditions, the input current can fall to zero (or below), non-linear carrier control tends to be unsuitable for use under light load conditions. In addition, because there is no provision o reduce the input current when the effective input voltage level increases, such non-linear carrier control tends to be unsuitable where the line voltage can vary in amplitude.
Accordingly, there is a need for an improved switching power supply. It is toward these ends that the present invention is directed.
The present invention is a switching power supply which uses carrier control and input voltage sensing. In one aspect, an output voltage is monitored to form a carrier signal. The carrier signal is compared to a signal that is representative of the input current in order to control the switching duty cycle. In addition, a signal representative of the input voltage is summed with the signal that is representative of the input current, or with the carrier signal, in order to effectively control the switching duty cycle under light load conditions and conditions in which the effect input voltage level can vary. Thus, the invention substantially obtains advantages of prior power factor correction techniques without significant drawbacks.
These and other aspects of the invention are explained in more detail in the following detailed description, accompanying drawings and appended claims.